1. Field of the Invention
The present invention relates to a semiconductor device, a circuit in which is isolated and insulated by an isolating region.
2. Description of the Related Art
A semiconductor device shown in FIG. 10A is proposed. In the proposed device, an SOI substrate 200 includes a base silicon layer 200b, an active silicon layer 200c, and an insulating layer 200a that separates the silicon layers 200b, 200c, as shown in FIG. 10B. The active silicon layer 200c includes a power device area S, where an output power device such as a UPDRAIN or an LDMOS is located, and an on-chip circuit area T, where an on-chip circuit that generates reference voltage is located. The power device area S is surrounded by a trench 200d and an insulating material 201a, which is located in the trench 200d. The on-chip circuit area T is surrounded by another trench 200e and another insulating material 201b, which is located in the trench 200e surrounding the on-chip circuit area T.
The active silicon layer 200c includes a plurality of n+-type contact regions 202 between the power device area S and the on-chip circuit area T to fix the potential, as shown in FIGS. 10A and 10B.
The active silicon layer 200c also includes a field ground (F/G) area 203. The field ground area 203 and each n+-type contact region 202 are electrically connected by a wiring line 204.
In the proposed device, the output power device and the on-chip circuit are insulated and electrically separated from each other by the insulating layer 200a and the insulating materials 201a, 201b, as shown in FIG. 10B. However, when the output power device is switched with relatively high frequency, an electrical noise is generated due to the variation in counter-electromotive force or load current generated by inductive load (L load) in the output power device. The noise can prevent the on-chip circuit from functioning properly. The influence of the noise can be attenuated by increasing the distance between the output power device and the on-chip circuit. However, the size of the SOI substrate 200 increases.
The present invention has been made in view of the above aspects with an object to provide a semiconductor device having a structure, with which the influence of an electrical noise, which is generated by an output power device, on an on-chip circuit is suppressed.
In the present invention, the output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise, which is generated by the output power device, is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.